DS1123L
3.3V, 8-Bit, Programmable Timing Element
12
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IN do not benefit from the REF output’s tendency to track
OUT over temperature and voltage. Figure 9 shows INL’s
effect on delay performance graphically.
Configuring the DS1123L as a Monostable
Vibrator or PWM
To configure the DS1123L as a monostable vibrator, set
MS = 1. This causes the reference output (PWM) to be
set high between tREF and tD when it is triggered by the
input. After time period tD has elapsed, the output
returns low, and the monostable vibrator can be retrig-
gered. See Figure 10 for the timing of the OUT and
PWM signals. When MS = 1 and the DS1123L is trig-
gered by an external free-running oscillator, reference
output becomes a pulse-width modulator (PWM). When
using the DS1123L as a PWM, the free-running oscillator
should not be generated by connecting OUT to the input.
This causes the PWM period to change in addition to the
duty cycle as different values are programmed, which is
most likely not the desired functionality.
The minimum pulse width that can be practically gener-
ated is approximately 5ns. This is because a 5ns pulse
is approximately the shortest pulse that can be pro-
duced with the DS1123L’s output driver. The mono-
stable vibrator cannot be retriggered, so subsequent
triggering pulses into IN should not be present until
after the output has returned low.
Configuring the DS1123L as an Oscillator
To configure the DS1123L as an adjustable oscillator,
set MS = 1 and externally connect OUT to IN. Setting
MS = 1 by itself inverts the input signal in addition to
delaying it (see Figure 10). Connecting OUT to the
input then causes the circuit to oscillate with the period
being twice the programmed delay. Table 2 shows the
oscillator frequency ranges that the different speed
grades of DS1123Ls provide.
REF
IN
OUT
REF
IN
OUT
DS1123L
tWI
tREF
tD0
tDMAX
Figure 7. Reference Delay Timing, MS = 0
DELAY
tDMAX
tREF
tREF0
tDREF
STEP
255
0
tD0
Figure 8. Delay Parameters
STEP
LINE FIT BETWEEN
MEASURED MAX
AND MIN DELAY
MEASURED DELAY
FOR ALL STEPS
0
64
128
192
255
INL
EXAGGERATED
DELAY
MEASURED
tDREF
MEASURED
tD0
tREF
Figure 9. Integral Nonlinearity
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